1. Field of the Invention
The present invention relates to a signal converter and a method for converting a start signal to an end signal, and in particular the present invention relates to a signal converter and a method for converting a start signal to an end signal which may be employed using digital signal-processing components in telecommunications or high-frequency technology.
2. Description of the Related Art
In telecommunications, to shift a signal from a current frequency (current frequency) into a higher transmission frequency (target frequency) mainly mixers are used. For such a shifting, for example in the transmitter several different possibilities are possible. First, a signal having a low bandwidth Blow may be shifted to different center frequencies within a large bandwidth B. If this center frequency is constant over a longer period of time, then this means nothing but the selection of a subband within the larger frequency band. Such a proceeding is referred to as “tuning”. If the center frequency to which the signal is to be shifted varies relatively fast, such a system is referred to as a frequency-hopping system or a spread-spectrum system. As an alternative, also within a large bandwidth B several transmission signals may be emitted in parallel in the frequency multiplexer with a respectively low bandwidth Blow.
Analog to these proceedings in the transmitter, the respective receivers are to be implemented accordingly. This means on the one hand that a subband of the large bandwidth B is to be selected when the center frequency of the transmitted signal is constant over a longer period of time. The tuning is then performed to the predetermined center frequency. If the center frequency is varied relatively fast, as it is the case with a frequency-hopping system, also in the receiver a fast temporal change of the center frequency of the transmitted signal has to take place. If several transmit signals have been sent out in parallel in the frequency multiplexer, also a parallel reception of those several frequency-multiplexed signals within the larger bandwidth B has to take place.
Conventionally, for an above-indicated tuning system and a frequency-hopping system an analog or digital mixer is used, wherein the digital mixing conventionally takes place with one single mixer stage. In an analog mixer, a high expense in circuit technology is necessary, as for a precise mixing to the target frequency highly accurate mixer members are required which substantially increase the costs of the transmitter to be manufactured. It is to be noted with regard to a digital mixer that in certain respects a high expense in terms of circuit engineering (or numerics, respectively) is required when the signal is to be mixed onto a freely selectable random target frequency.
For a parallel transmitting and receiving of several frequency sub-bands, further frequently the OFDM method (orthogonal frequency division multiplexing) and related multicarrier or multitone modulation methods, respectively are used. The same require, by the use of the Fourier transformation, a partially substantial computational overhead, in particular if only a few of the frequency sub-bands from a large frequency band having several individual frequency sub-bands are required.
Conventional mixers may here be implemented in a similar way to the mixer device 2400, as it is illustrated in FIG. 24A, wherein this mixer device 2400 is related to a downconversion. Without limitation of generality, however, also a corresponding arrangement of the components of the mixer device illustrated in FIG. 24A may be used for an upconversion, however. Such a mixer device is illustrated in FIG. 24B.
The mixer device 2400 in FIG. 24A may comprise a mixer 2402, a low-pass filter 2404 and a downsampler 2406. The mixer 2402 includes an input 2408 for receiving a signal 2410 to be mixed. Further, the mixer 2402 includes an output 2412 for outputting the signal 2414 converted from the current frequency to a target frequency, which is supplied via an input 2416 of the low-pass filter 2404 to the same. Further, the low-pass filter 2404 includes an output 2418 for outputting a frequency-converted low-pass filtered signal 2420 which may be supplied via an input 2422 of the downsampler 2406 to the same. The downsampler 2406 includes an output 2424 for outputting a downsampled signal 2426, which is simultaneously an output signal output by the mixer device 2400. In FIG. 24B, components are illustrated corresponding to the mixer 2402, the low-pass filter 2404 and the downsampler 2406, wherein in the interconnection according to FIG. 24B an upconverter 2400a is realized. With regard to this, the order of the components was changed such that first an upsampler 2406a corresponding to the downsampler 2406 for an upconversion is connected upstream to the low-pass filter 2404 and downstream from the mixer 2402. The functionality of the mixer 2400a illustrated in FIG. 24B may be explained analog to the subsequent functionality of the mixer 2400 which is described in more detail, wherein the mixer 2400a shown in FIG. 24B is implemented to cancel an effect of the mixer 2400 of FIG. 24A on a signal.
If the input signal 2410 with the current frequency is supplied to the mixer device 2400 in FIG. 24A, wherein the start signal 2410 is based on a first sampling frequency defining an interval of two time-discrete signal values, then the mixer 2402 performs a conversion of the current frequency to an intermediate frequency, from which the intermediate frequency signal 2414 results. In this intermediate frequency signal 2414, only the frequency on which the start signal 2410 is located (i.e. the current frequency) is converted to an intermediate frequency, wherein the sampling frequency is not changed by the mixer 2402. With a suitable selection of the current frequency and the sampling frequency, in a simple way in terms of numerics or circuit engineering a mixing to the intermediate frequency signal 2414 having the intermediate frequency may be realized. If, for example, the spectral interval between the current frequency and the intermediate frequency is one quarter of the sampling frequency in its magnitude, then a mixing may be performed by a multiplication with the values 1, i, −1 and −i or by a negation of real part or imaginary part value, respectively, of the start signal 2410 and by an exchange of real and imaginary part values of start signal values of the start signal 2410. Such an approach which may be easily implemented with regard to numerics or hardware technology, is, for example, disclosed in Marvin E. Frerking, Digital Signal Processing in Communication Systems, Kluwer Academic Publishers.
Hereupon, a low-pass filtering of the intermediate frequency signal 2414 with the first sampling frequency takes place by the low-pass filter 2404, whereupon a low-pass filtered intermediate frequency signal 2402 results which is again based on the first sampling frequency. By the downsampler 2406 then a downsampling of the low-pass filtered intermediate frequency signal 2402 takes place, whereupon a reduction of the sampling frequency results without again spectrally converting the signal.
Such an approach of a mixer 2402 which may easily be realized in terms of numerics or circuit engineering has the disadvantage that by the predetermined connection between the current frequency and the sampling frequency only intermediate frequencies may be obtained which are arranged in a spectral interval of a quarter of the sampling frequency around the current frequency. This reduces the applicability of such a mixer 2402 which may efficiently be realized in terms of numerics or circuit engineering. If also intermediate frequencies are to be obtained, which comprise another interval to the current frequency than a quarter of the sampling frequency, a multiplication of the individual start signal values of the start signal 2410 with the rotating complex pointer ej2πkfc/fe is necessary, wherein k is a running index of the start signal values, fc is the desired center frequency (i.e. the intermediate frequency) and fs is the sampling frequency of the signal. It is to be considered, however, that in the multiplication of the start signal values with the rotating complex pointer not only purely real or purely imaginary multiplication factors, respectively, are to be used, but that the multiplication factors used comprise real and imaginary parts. By this, a solution efficient in terms of numerics and circuit engineering as it was indicated above may not be used. A mixer would be desired, however, which offers the possibility to perform a mixing of start signal values from a current frequency to any intermediate frequency in an efficient way in terms of numerics and circuit engineering.
Further, also a concept similar to downsampling may be realized for a spectral mixing using upsampling. A frequency converter or signal converter based on this concept is, for example, illustrated in FIG. 25 by the illustrated signal converter 2500. The signal converter 2500 illustrated in FIG. 25 further comprises the possibility to upsample and subsequently spectrally convert different start signals. Hereupon, a merging of the upsampled and spectrally converted start signals to a common end signal takes place.
In order to provide such a functionality, the signal converter 2500 comprises a first input 2502 for receiving a first start signal xplus[k], a second start signal input 2504 for receiving a second start signal xzero[k] and a third start signal input 2506 for receiving a third start signal xminus[k]. Further, the signal converter 2500 comprises a plurality of zero inputs 2508 for providing the signal converter with the value 0. In addition, the signal converter 2500 comprises a first multiplexer 2510, a second multiplexer 2512, a third multiplexer 2514, a fourth multiplexer 2516, a fifth multiplexer 2518 and a sixth multiplexer 2520. Additionally, the signal converter 2500 comprises a first demultiplexer 2522, a second demultiplexer 2524 and a third demultiplexer 2526. Further, the signal converter 2500 includes a first low-pass filter LP1, a second low-pass filter LP2 and a third low-pass filter LP3. Finally, the signal converter 2500 includes an adder 2528 for adding an output signal of the fourth multiplexer 2516, an output signal of the fifth multiplexer 2518 and an output signal 2534 of the sixth multiplexer 2520 to provide an end signal y[m]. Apart from that, the signal converter 2500 comprises a first processing means 2536, a second processing means 2538 and a third processing means 2540. Each of processing means 2536, 2538 and 2540 comprises four partial processing means 2542 which are implemented to perform a complex multiplication of an input signal with a complex multiplication factor.
The signal converter 2500 is interconnected such that by the first multiplexer to an input of the first low-pass filter LP1 a sequence consisting of a sampling value of the first start signal xplus[k] and a sequence of three consecutive zero values is supplied. An output of the first low-pass filter LP1 is connected to the first demultiplexer 2522. The first demultiplexer 2522 is implemented to allocate the low-pass filtered signal received from the first low-pass filter LP1 in temporal order first to a first partial processing means of the first processing means 2536, then to a second partial processing means and subsequently to a third partial processing means and finally to a fourth partial processing means. The first partial processing means here is implemented to perform a multiplication of a signal value with the factor 1, which may be realized in circuit engineering in particular by the fact that a signal is left unchanged in the first partial processing means. The second partial processing means is implemented to multiply a signal with the complex value j, while the third partial processing means is implemented to perform a negation of a signal. Further, the fourth partial processing means is implemented to perform a complex multiplication of a signal value with the factor −j. Further, the fourth multiplexer 2516 is connected to the first processing means 2536 such that in a temporally subsequent order first a signal processed by the first partial processing means, then a signal processed by the second partial processing means and then a signal processed by the third partial processing means and finally a signal processed by the fourth partial processing means is multiplexed to the output signal 2530 of the fourth multiplexer 2516. Analog to the above-described interconnection of the first multiplexer 2510 with the first low-pass filter LP1, the first demultiplexer 2522, the first processing means 2536 and the fourth multiplexer 2516 in the first processing branch also the second multiplexer 2512, the second low-pass filter LP2, the second demultiplexer 2524, the second processing means 2538 and the fifth multiplexer 2518 may be interconnected. In contrast to the interconnection in the first processing branch 2544, in the second processing branch 2546, however, the second start signal xzero[k] is multiplexed to the second low-pass filter LP2, while each of the partial processing means of the second processing means 2538 are implemented to perform a multiplication with the factor 1. In other words, this means that in the partial processing means of the second processing means 2538 no change of the signal needs to be performed. The second processing means 2538 may thus also be regarded as redundant and is only indicated in FIG. 25 for reasons of clarity of illustration to enable a better understanding of a signal processing in the first processing branch 2544 and in the third processing branch 2548.
Analog to the interconnection of the components in the first processing branch 2544, also an interconnection of the components in the third processing branch 2548 may be described. Here, by the third multiplexer 2514 either a value of the third start signal xminus[k] or one of three consecutive zero values is supplied to the third low-pass filter LP3. Hereupon, a signal output by the third low-pass filter LP3 is laid onto a first, second, third or fourth partial processing means of the third processing means 2540 by the third demultiplexer 2526. Here, the first partial processing means is implemented to perform a multiplication with the value 1, the second partial processing means is implemented to perform a multiplication with the value −j, the third partial processing means is implemented to perform a negation of the signal value and the fourth partial processing means is implemented to multiply a signal value with the value j. Further, an output value of the first, second, third or fourth partial processing means is sequentially multiplexed to the output 2536 of the sixth multiplexer 2520 by the sixth multiplexer 2520.
The mode of operation of such a signal converter 2500 may be described as follows. First, the first start signal xplus[k] is applied to the first input 2502 and multiplexed by the first multiplexer 2510 such that a sequence consisting of a value of the first start signal xplus[k] and three subsequent zero values (i.e. of the value 0) is supplied to the first low-pass filter LP1 in the first processing branch 2544. Here, the first multiplexer 2510 usually comprises a clock or multiplex rate corresponding to four times a sampling rate of the first start signal. By this, between each sample of the first start signal three zeros are inserted, which leads to an upsampling of the signal. In the first low-pass filter LP1 of the first processing branch 2544 now, for example, on the basis of an FIR filter regulation a low-pass filtering of the upsampled signal takes place in order to suppress resulting image frequencies by upsampling. The low-pass filtered upsampled signal is now subsequently supplied to the first demultiplexer 2522 which supplies the low-pass filtered signal to the partial processing means 2542 of the first processing means 2536 using the high, i.e. four times the sampling frequency as compared to the sampling frequency of the start signal. In the individual partial processing means 2542 of the first processing means 2536 now the multiplication of a signal supplied to the partial means takes place with a multiplication factor. The multiplication factors in the individual partial processing means are here selected such that considering the splitting up of the low-pass filtered signal by the first demultiplexer 2522 and the fourth multiplexer 2516 down-connected downstream from the partial processing means 2524 a signal results at the output 2530 of the fourth demultiplexer 2516 corresponding to an up-converted low-pass filtered signal. The spectral interval between the low-pass filtered signal and the up-converted low-pass filtered signal at the output 2530 of the fourth multiplexer 2516 is here a quarter of the high sampling frequency, i.e. of four times the sampling frequency of the first start signal xplus[k].
An analog processing of the second start signal xzero[k] further takes place in the second processing path 2546, wherein again by the second multiplexer 2512 an insertion of zero values and thus an upsampling of the second start signal xzero[k] takes place. This upsampled signal is now supplied to the second low-pass filter LP2 for removing the image frequencies which resulted from upsampling. In the following, again by the second demultiplexer 2524, the splitting up of the low-pass filtered signal to the partial processing means is performed, wherein a weighting of a signal value with the value 1 takes place. As it was already explained above, such an operation in connection with the function of the second demultiplexer 2524 and the function of the fifth multiplexer 2518 corresponds to a direct “connection” of the low-pass filtered signal onto the output 2532 of the fifth multiplexer 2518.
Analog to the functioning of the signal processing in the first processing path 2544 and the second processing path 2546, now a processing of the third start signal xminus[k] in the third processing branch 2548 takes place. Here, again by the third multiplexer 2514 the third start signal is upsampled, wherein between each sample of the third start signal three zero values are inserted. The thus upsampled third start signal is now low-pass filtered in the third low-pass filter LP3 in order to suppress the image frequencies which resulted by upsampling. Analog to the functioning of the first demultiplexer 2522, the first processing means 2536 and the fourth multiplexer 2516 in the first processing branch 2544, by the third demultiplexer 2526, the third processing means 2540 and the sixth multiplexer 2520 a spectral conversion of the signal low-pass filtered by the third low-pass filter LP3 takes place. By the fact that now in the individual partial processing means of the third processing means 2540 the multiplication factors 1, −j, −1 and j are used in the indicated order, the signal applied at the output 2534 of the sixth multiplexer 2520 corresponds to a signal down-converted by a quarter of the (high) sampling frequency, as it is applied at the output of the third low-pass filter LP3. By the downstream adding means 2528 now the (up-converted) signal applied at the output 2530 of the fourth multiplexer 2516, the signal applied at the output 2532 of the fifth multiplexer 2518 and the (down-converted) signal applied at the output 2534 of the sixth multiplexer 2520 are added. From this, an end signal y[m] results having the possibility to simultaneously send out information on a first (high), a second (intermediate) and a third (low) frequency band. Here, in the first frequency band information of the first start signal xplus[k], in the second frequency band information of the second start signal xzero[k] and in the third frequency band information of the third start signal xminus[k] is contained.
Such a signal converter 2500 has the advantage that this way, in a relatively inexpensive way by the use of the first processing means 2536, the second processing means 2538 and the third processing means 2540, an efficient spectral conversion may be performed. It is a disadvantage of the signal converter 2500, however, that for a realization, as it is illustrated in FIG. 25, a number of nine multiplexers and demultiplexers is required. Thus, a circuit structure as it is illustrated in FIG. 25 requires a high wiring expense and simultaneously a lot of room on an integrated circuit, whereby manufacturing costs of such a signal converter are increased.